how to minimize the interconnect while doing synthesis?

[duffrose]

For some process, like 1P3M, the interconnect is limited by metal layer. Only metal 2 and metal 3 can be used as interconnect. So while doing synthesis, it is important to reduce the interconnect. Otherwise the interconnect may be the bottleneck for APR. How to do it in Design Compiler? Some suggestion or advice is welcome, thank you.

 

[mohaddin]

Hi
u r waste fellow, how metals come into picture in Logic synthesis.

Regards
Mohi

 

[skyismylimit]

Really a good question.. Few years back synthesis was done without the knowledge of the physical world, now we feel that not the case.. To have more prediction we need to do the synthesis physical aware. Thats the reason Design compiler Topographical (DCT) came into market addressing it. DCT = DC + some amount of placement engine.
Later they added some amount of clock tree algorithm to effectively calcuate the power. And very recently they have come up with some new DC graphical to do synthesis congestion aware.

To run it is very simple-- compile_ultra -scan -congestion.
and you can use report_congestion to report the GRC based congestion report.

*** You might need some extra license to run it.

If you need more info about this you can find some slides on this from tutorials sessions of SNUG san jose 2008.

Hope this helps

 

[duffrose]

Thank you skyismylimit, you guide the way to solve that problem. I hope with some DC script modification can reach the minimum interconnect.