How to minimize glitch in Verilog RTL coding ?

Status
Not open for further replies.

lostin_eda

Newbie level 6
Joined
Aug 16, 2007
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,366
How to minimize glitch in Verilog RTL coding.

thanks for your reply
 

Re: minimize glitch

one way to reduce glitch in sequential circuits is to avoid asynchronous reset's being used by the signals internal to the design...
 

minimize glitch

well try to write a verilog code where delay balancing is possible during synthesis, and balance the delay during synthesis
 

minimize glitch

Use A Flip Flop for the output

Now glittc will occur but your output will be clean
 

minimize glitch

first u should know why remove glitch?
some glitch don't arise problem, and all combinational logic has glitch.
 

Re: minimize glitch

Dear Dude,

Usually synchronizing flip flops constantly battle for

metastability and glitching inputs.

try to use moore circuit,

avoid cross talk, gated clocks,metastability.

these are some ways

santu
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…