How to minimize glitch in Verilog RTL coding ?

[lostin_eda]

How to minimize glitch in Verilog RTL coding.

thanks for your reply

 

[lordsathish]

Re: minimize glitch

one way to reduce glitch in sequential circuits is to avoid asynchronous reset's being used by the signals internal to the design...

 

[sumit_techkgp]

minimize glitch

well try to write a verilog code where delay balancing is possible during synthesis, and balance the delay during synthesis

 

[aajizattari]

minimize glitch

Use A Flip Flop for the output

Now glittc will occur but your output will be clean

 

[phoenixfeng]

minimize glitch

first u should know why remove glitch?
some glitch don't arise problem, and all combinational logic has glitch.

 

[santuvlsi]

Re: minimize glitch

Dear Dude,

Usually synchronizing flip flops constantly battle for

metastability and glitching inputs.

try to use moore circuit,

avoid cross talk, gated clocks,metastability.

these are some ways

santu