How to measure the Q factor and Leakage of pmos decaps

[maxy_spy]

Hello,
I am trying to measure the leakage of a pmos decap and also calculate the Q factor of the same capacitor.

The test bench that I am creating is here:
https://obrazki.elektroda.pl/6656254200_1423229568.jpg

I wanted to know that is this test bench correct? Here, I have applied VDD = 1.2 at the gate of the PMOS ( for leakage the device should be turned off). I have applied another vdc between Source and Drain. I am measuring the node current with Dc analysis @ the source which will be my leakage current.

Is this correct approach? I saw that current I get in the .lib is in the order of nA and here it is in uA. also, I tried putting resistance between the source and the +ve terminal of the Vdc so that I could tune the resistance to get the leakage in nA. I am not sure if this is correct or not.

I have to make sure that the leakage here is correct.

I have no clue how I will have to measure the Q factor using Cadence.

Please help me with this. I would like to thank you in advance and I really appreciate your help.

Thank you

 

[AMS012]

If you are using pmos as decap, i think you should be looking at gate leakage rather. One would just tie the source and drain to ground for using a pmos as decap.

 

[maxy_spy]

If you are using pmos as decap, i think you should be looking at gate leakage rather. One would just tie the source and drain to ground for using a pmos as decap.

Thanks for the reply. So how do i connect to the gate? Do I have to use a VDC between the gate and the source or gate and drain?
the connection given is gate is connected to VSS and source and drain is connected to VDD in the symbol. So how can I solve this?

If i connect the gate to VDD for turning off the pmos. The gate leakage comes to 0 which is not correct

 

[AMS012]

yeah, you should connect the source and drain of the pmos to vdd (wrongly mentioned as ground in my previous post) and gate to vss and look at the gate leakage current by doing a dc simulation. There will be some leakage current flowing through gate depending on the length of the device (gate leakage current basically depends on the device technology node).
You can also calculate the actual cap value of the pmos by connecting a known resistance in series and doing an AC response and back calculating the cap value by 3dB frequency.
Another important thing to note is that the cap value varies with the bias voltage i.e changing gate voltage will change the cap value.

 

[dick_freebird]

A decoupling capacitor wants to be turned fully on at the
channel, the channel is your bottom plate. An "off" bias
gives you the inferior series value of Cox and Cdepletion.
Your gate will see full supply voltage. This is where you
want to check gate leakage. But it is very probable that
neither gate current of normal, nor defected devices is
going to be well represented in your SPICE model and
you owe it to yourself to check the PDK simulation release
notes about such known deficiencies.

Likewise your Q factor depends on the quality of this
aspect of the models. It's taken seriously in RF CMOS,
not so much (sometimes, simply not) in digital kits. You
ought to be able to figure the top gate resistance by
hand from technology data and aspect ratio. Things like
poly depletion and the whole bottom plate, variable
channel resistance mess, less so). Figure your bottom
plate net resistance ought to be about 1/4 of Ron,
since you are going from L/W to (1/2)*(L/2)/W for the
two shorter parallel paths. But of course Ron will vary
with VT, Tox, temp, etc.

Finger geometry is your primary degree of freedom
and this will be driven by the somewhat competing
Q and C/area interests. Use shorter L to drive R down
and Q up, but you eat more area devoted to the S/D
contacts between. A few test layouts and some
interpolation / extrapolation should lead you to the
sweet spot.

 

[maxy_spy]

A decoupling capacitor wants to be turned fully on at the
channel, the channel is your bottom plate. An "off" bias
gives you the inferior series value of Cox and Cdepletion.
Your gate will see full supply voltage. This is where you
want to check gate leakage. But it is very probable that
neither gate current of normal, nor defected devices is
going to be well represented in your SPICE model and
you owe it to yourself to check the PDK simulation release
notes about such known deficiencies.

Likewise your Q factor depends on the quality of this
aspect of the models. It's taken seriously in RF CMOS,
not so much (sometimes, simply not) in digital kits. You
ought to be able to figure the top gate resistance by
hand from technology data and aspect ratio. Things like
poly depletion and the whole bottom plate, variable
channel resistance mess, less so). Figure your bottom
plate net resistance ought to be about 1/4 of Ron,
since you are going from L/W to (1/2)*(L/2)/W for the
two shorter parallel paths. But of course Ron will vary
with VT, Tox, temp, etc.

Finger geometry is your primary degree of freedom
and this will be driven by the somewhat competing
Q and C/area interests. Use shorter L to drive R down
and Q up, but you eat more area devoted to the S/D
contacts between. A few test layouts and some
interpolation / extrapolation should lead you to the
sweet spot.

@dick_freebird Thanks a lot for the reply. I wanted to know how did you come up with this?
(1/2)*(L/2)/W. Also, the thing is that I have the decaps already made. I just have to figure out which one is better out of the available options. I was not able to simulate them for Q factor. after looking at your statement it looks like I have to calculate manually and figure out the Q factor

Thanks

 

[dick_freebird]

Rough approximation of resistance to the center cut-line of
the gate from one end is Rs*(L/2)/W. From both ends, two
in parallel halves this.

Now whether this exactly matches a finer-mesh figuring
or a proper closed form analysis, I somewhat doubt. Gut
method is what this is.

 

[maxy_spy]

Rough approximation of resistance to the center cut-line of
the gate from one end is Rs*(L/2)/W. From both ends, two
in parallel halves this.

Now whether this exactly matches a finer-mesh figuring
or a proper closed form analysis, I somewhat doubt. Gut
method is what this is.

@dick_freebird thank you for the explanation. I also wanted to know what is the correct way to measure the leakage in the Pmos? How should the connections be made? I am sorry i was unable to understand your 1st post regarding leakage measurement.
Did you mean that the pmos should be on for leakage measurement so I will have to connect the gate to VSS and source and drain to VDD? I thought that leakage happens when the device is turned off

 

[dick_freebird]

You care about the supply-supply leakage as you will apply
the device, not necessarily as someone else would in another
kind of circuit. G=VSS, {D, S, B}=VDD.

Any configuration will have conductance between any two
terminals. You care about only one configuration. You should
test it like you'll use it (including a look at worst cases and
margin against any destructive or degradation effects).

People will scowl at you if you put a whole mess of FET
gate area supply-supply. Good way to test the capability
of your ESD protection and your foundry's defect density.
It may be your only available option. But there is a price
for everything and this is a fragile capacitor relative to
most.