Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to measure hystersis and offset of a latched comparator?

Status
Not open for further replies.

mmohsen

Advanced Member level 4
Joined
May 19, 2005
Messages
100
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,298
Activity points
2,425
offset latched comparator

Can anyone till me how to measure the hystersis and offset of the latched comparator (test bench ?)

Regards
 

Re: Latched comparator

In order to measure offset and delay :

1. Vref = fix dc voltage = Full swing voltage/2 or usually VDD/2

2. Vin = ramp the input from 0 full voltage swing @ VDD

Run the simulation and then u will see the output response that it change from 0V to VDD ( digitally = from logic 0 to logic 1 ).

The distance of the point where Vin and Vref intercept to the actual rise of the vout from 0 to VDD is the offset or maybe just the delay.
 

Re: Latched comparator

For the Offset:
----------------
In general in simulation u will not find them unless u put some device mismatch in the circuit. Still if the design is having some systematic offset u could find them in the following way. The same applies when u give some mismatch and looking for the random offset coming from mismatch (this is a potential contributer). As u are talking of latched comparator the following applies to that only.

The offset is DC char. of a comparator. It could be measured as syukri has mentioned. But you have to run a long simualtion for the clock speed is higher. The other way is like following.
Give a DC voltage at V=+ (say ICRM- + (ICMR/2)). Now give V- a DC = V+ and run transient simulation. It will give either "1" or "0". Now go on incraesing the DC voltage for V- in step, i.e., say 1mV above/ below the previous voltage and again run simulaiton. Once you are getting a transition, try to fine tune the place by above/below 100uV and then 10uV and again simulation. The simualtions will not take much time. Now you will be getting a point where the comparator is transiting from 0->1 and vice versa.

If the two transion point are exactly centered abot V+ (= Vref) then no offset. Other wise offset is there. Now from the above three voltage levels (Vref, Vpt=> where it transits to 1 and Vnt; these are magnitude not the actual voltage level) you can calculate Offset and Minimum resolution.

Not to verify the above calculation; you give V+ same as Vref and give a square wave having zero and one state equal to the Vpt and Vnt above. The comparator now should change between 0 and 1. But unless you add the offset to either V+ or V-; it won't. Now you add the offset as calculated and watch for it.

Theoritically the square wave sould have same magnitude below and above as minimum resolution for +ve going and -Ve going is generally same.

Hysteresis:
------------
Alsmos in the same way. Just check the two transition points and difference from the V+ or centre. Hyst. = Vpt-Vnt.



The method above I followed my self and calculated in that way. I don't know whether you can can get it clearly.
gd luck...
sankudey
 

    mmohsen

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top