[SOLVED] How to manipulate signals within certain time period in testbench in modelsim?

[nervecell_23]

For instance, I want to figure out how many times SignalA becomes active during 100ns and 200ns, instead of counting in the waveform, how to achieve it by HDL in the testbench?

I need to set up a counter first, then how to make it count only within a specified time period?

Thanks!

 

[rca]

used this rising of falling edge of your signal as clock to increment your counter.

- - - Updated - - -

in verilog you could used variable $now to know when you could enable your counter.

 

[dave_59]

Assuming your timescale is 1 ns in Verilog

integer counter;
initial begin
           count = 0;
           fork
            #100 begin : counter
                       forever @(posedge SignalA) count = count + 1;
                    end
            #200 disable counter;
          join
          $display("SignalA went high %0d times", count);
        end

This would be slightly easier in SystemVerilog which ModelSim does support

int counter;
initial begin
           count = 0;
           fork
            #100ns forever @(posedge SignalA) count++;
            #200ns;
          join_any
          disable fork;
          $display("SignalA went high %0d times", count);
        end