You might be using some coregen components. While u are generating the core it also gives a .vhd file and .vho file along with .edn. Read the comments in those files and instantiate them in some top-level component. Yes, They can be simulated.
yes edn files are generated by xoregen....if u want to simulate then coregen also generates .vhd and .v files which r present in ur working directory... u can include these files in ur modelsim project and simulate if xilinx coregen libraries are complied in modelsim....an easier way is invoke modelsim from ur xst.
Hi guys
Thank you for the reply but i am not sing any coregen files.
I just downloaded some core from the net which gave me this .edn file.
when i included in my project it simulates but it is not been identified in sources in project window.
Yes, they are not identified in source window under device, but under project. That is because only .vhd & .v can be seen as design files which can be synthesized.
.end files are EDIF Implementation Netlists for a core. These files describe how the core is to be implemented. They are already synthesized netlists.
Thanks for that.
But is it possible to simulate it in modelsim.
Can modelsim understands the behavior of the core since it is treated as black box. What I should do to get the proper simulation results? Any supporting files needed !!!
Hi Sandeep,
Yes, it is possible to simulate these in Post-Synthesis simulation. But you will have to compile the Unisim & Simprim libraries in your ModelSim usin 'compXlib' command. This link will be useful to understand that.
**broken link removed**