above 3 is the max value,its average value is around 1.2,is it high?if it is,is there any way to lower it?
3
% RMS is ok for GSM/EDGE. 3
degrees max is not
terrible, but could probably be improved.
Maybe is it a GSM signal ?. If you are using an IQ modulator check :
i) Check phase and amplitude balance of the modulator : unwanted
sideband should be <40dBc as should the unwanted carrier frequency
otherwise phase error will be higher than predicted.
ii) If VCO is separate to the IQ mod, replace VCO with signal generator.
If phase error improves then the VCO could be being
pulled by the output of the IQ mod : check layout and
buffering of the VCO output(reverse isolation), check VCO control
line layout. If VCO is in same asic then try reducing modulator
power output or match and see what happens.
iii) PLL loop bandwidth may be too wide : the wider the PLL
bandwidth is, the higher the phase error will be as the phase
error at the IQ output is partly due to the phase noise of the
PLL.
iv) Check PA power control loop circuitry : could be feeding back
RF power and/or harmonics back to the VCO.
Good Luck with the bug hunt !
3% RMS phase error from the source into PA is too much. Should be less than 0.5%
Not really, the PA should not contribute significant phase error to a
GSM signal, therefore 3% RMS phase error is ok (for GSM and
EDGE). O.5% is excellent and requires low noise local oscillators.
3 Degrees RMS on the other hand would be a bit high..