how to make the phase error lower?

[hypear]

my cell has high phase error: peak about 16
rms about 5
i tried to change its pa's power line and its output mathing,but it doesn't work.please give me some advice .
thanks

 

[toonafishy]

Make sure the RF from the output of the PA is not getting into the VCO.

 

[xinxin]

You must make sure:
a. the power to the PA
b. PA output matching
c. PA input matching
d. T/R switch
e. RF layout , especially PA and Power , GNS

 

[hypear]

thanks for your reply
i also have some questions:
1 how to tune the match? is there any way to decide the range of the match? use vector network?
2 the input power of pa is enough,but its phase error is about 3,is it higher? if it is ,how can i do?
thanks

 

[vfone]

3% RMS phase error from the source into PA is too much. Should be less than 0.5%. Could be layout, power supply, feedback, phase noise, etc.
regards

 

[hypear]

above 3 is the max value,its average value is around 1.2,is it high?if it is,is there any way to lower it?
thanks

 

[martinthorn]

above 3 is the max value,its average value is around 1.2,is it high?if it is,is there any way to lower it?

3% RMS is ok for GSM/EDGE. 3degrees max is not
terrible, but could probably be improved.

Maybe is it a GSM signal ?. If you are using an IQ modulator check :

i) Check phase and amplitude balance of the modulator : unwanted
sideband should be <40dBc as should the unwanted carrier frequency
otherwise phase error will be higher than predicted.

ii) If VCO is separate to the IQ mod, replace VCO with signal generator.
If phase error improves then the VCO could be being
pulled by the output of the IQ mod : check layout and
buffering of the VCO output(reverse isolation), check VCO control
line layout. If VCO is in same asic then try reducing modulator
power output or match and see what happens.

iii) PLL loop bandwidth may be too wide : the wider the PLL
bandwidth is, the higher the phase error will be as the phase
error at the IQ output is partly due to the phase noise of the
PLL.

iv) Check PA power control loop circuitry : could be feeding back
RF power and/or harmonics back to the VCO.

Good Luck with the bug hunt !

3% RMS phase error from the source into PA is too much. Should be less than 0.5%

Not really, the PA should not contribute significant phase error to a
GSM signal, therefore 3% RMS phase error is ok (for GSM and
EDGE). O.5% is excellent and requires low noise local oscillators.
3 Degrees RMS on the other hand would be a bit high..

 

[hypear]

thanks for your advice .
1.we use transceiver of infieon's,so vco is integrated in it,i can't change it
2.we use rf3110,it needn't pa power control
3.you say to make the pll's BW lower,will it influence its capture character
so i want to know what influences cell's phase error(peak and rms)
please help me

 

[martinthorn]

So an Infineon RFIC and an RFMD PA..

Ok, a few other possibilities :

i) Output of the IQ modulator may not 'like' the input
inpedence of the PA : try an attenuator and/or buffer
between them to see what happens..

ii) Check layout for RF tracks close to supplies/control
lines/reference clock lines.

iii) Ensure the PCB is well grounded with plenty of
grounding vias everywhere.

iv) Check that the power ramp control line from baseband
is correct and noise free.

v) Try different/more decoupling capacitor values on the
RFIC and PA supplies

3.you say to make the pll's BW lower,will it influence its
capture character

It can do, but it is possible to keep the same settling time
and decrease loop BW by reducing the PLL damping (lose a few
degrees of phase margin though).

Good luck (again!)

 

[yakult]

Hi,

Pls check the IQ balance and the isolation between VCO and PA.

Yakult

 

[mckinson]

match PA output inpedance , avoid the power
feedback to the trancevier to cause the VCO frequency pulling

 

[vfone]

I don’t agree with martinthorn
3% RMS phase error from the source is too much even for GSM. For EDGE is deadly.
Try first to find the reason of this high source RMS phase error.
regards