how to make the Pass device of LDO ?

[fanrong]

LDO and LDMOS ?

Hi everyone :

I am designing a LDO IC with input voltage from 3 - 12V . Does the pass device need to be made by LDMOS ?
Does anyone know the development history of LDMOS such as how long ago the
DMOS process was taken into the LDO IC productions , and which IC corp's
LDO and which LDO productions take LDMOS processs ?
Someone tell me LDMOS decrease the pass device's on resistence . IS it true ?
Does the LDMOS LDO's short circuit protecting and current limiting are different
from the LDO's with normal process ?

Added after 17 minutes:

Another questions :
For the pass device 's layout is compact , how
to connecting the substrate bias , for example ,if
the pass device is PMOS , how to bias the substrate
to supply .
Does the LDMOS will make the question easy ?

Added after 15 minutes:

What is the difference between the LDMOS and
CMOS , such as threshold voltage ,current-voltage
relation ?
Some one tell me most LDMOS's gate is enclosed
or the transistor's is layouted like grid . Is it true ?
If so ,why ?

 

[hung_wai_ming@hotmail.com]

LDO and LDMOS ?

There are already many CMOS process which can support HV for at least 12V as Flash macro needs 12.5V for charge pump, so you may not need LDMOS.
Sorry that I don't know LDMOS. Cannot give further help. If u need help on LDO design, we can share instead

 

[fanrong]

Re: LDO and LDMOS ?

Thanks for your response !

Some people tell me LDMOS can decrease the on-resisttence of
the pass device . But some other people said it is not necessay .
So I need the suggestion from some one who designed LDO .

 

[haff99]

In general, DMOS devices have a better RDSonA then a NMOS or PMOS devices(for a similarly voltage rated device). Therefore you get a lower resistance device for the same area with a DMOS as opposed to a NMOS or PMOS. Thats why you see DMOS devices used for large swithces with very lowe RDSon.

As for some of your other questions, if you have to use a LDMOS for your pass device, well that really depends on the Vth and output voltage you expect. IF you want 3V in and 2.8V out, well you need to generate some higher voltage to drive the gate. In some of the processes I have worked on the Vth of the LDMOS devices is higher then an equivalent voltage rated NMOS device. Even with the higher VT the Ron is typically much less with the DMOS. So if you need 2.8V out from 3V and you don't want to add a charge pump or something like that, a PMOS switch is the way to go.

So it really all depends on your design needs and what the process parameters are of your LDMOS devices.

 

[aryajur]

Hello haff,
Why is the RdsON of a DMOS better than a conventional MOS? A DMOS has a lightly doped drain (drift) region and that should worsen the RdsON of the device? Could you please explain a bit more about it? Thanks.

 

[haff99]

I am not a process guy, so I don't want to get into all the diffusions and stuff. In general, as you increase the voltage rating on a NMOS device the minimum gate lenght keeps larger and larger, thus having the effect of lowering the RDSon. However, with the DMOS device, the way it fabricated, the gate lenght usually ends up being much smaller for a similiarly voltage rated NMOS device. The gate lenght ends up being a huge factor in the RDSon calculations

You start to see the benefits more and more as you increase the voltage rating of your device. Once you start getting above 20V VDS rated devices(at least in the processes I have worked on), you start to see the DMOS RDSon being much lower then an NMOS device of the same area.

 

[aryajur]

I see, that makes sense, to compare a NMOS and DMOS of the same voltage rating, I was thinking otherwise.

 

[fanrong]

So how about LDO with Vin=12 , Io=400mA , Ron=1 ?