how to make the code synthesizable?

[ammassk]

dear all,
I have written a code as shown below. I couldn't make it synthesazable. I don't understand how to make it synthesizable also. PLease help me to do the same.
/code
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bitnode is
port(clk,wr:in std_logic;
op0,op1,op2,op3,op4,op5,op6,op7,op8,op9,op10,op11,op12,op13,op14,op15ut std_logic_vector(15 downto 0));
end bitnode;

architecture Behavioral of bitnode is
signal m,n:integer;
type rowarray is array(0 to 15)of std_logic_vector(15 downto 0);
signal rowmem:rowarray;
type bitarray is array(0 to 15)of integer;
signal node:bitarray;
type array1 is array(0 to 7)of std_logic_vector(15 downto 0);
signal we:array1;
type array2 is array(0 to 7)of std_logic_vector(15 downto 0);
signal pr:array2;
signal done:std_logic;
begin
process(wr)
begin
if wr='1' then
node(0)<=1;
node(1)<=3;
node(2)<=4;
node(3)<=7;
node(4)<=0;
node(5)<=1;
node(6)<=2;
node(7)<=5;
node(8)<=2;
node(9)<=5;
node(10)<=6;
node(11)<=7;
node(12)<=0;
node(13)<=3;
node(14)<=4;
node(15)<=6;
rowmem(0)<="1111101111000001";
rowmem(1)<="1111010001110111";
rowmem(2)<="1111101111000001";
rowmem(3)<="1111101111000001";
rowmem(4)<="1111101111000001";
rowmem(5)<="1111101111000001";
rowmem(6)<="1111001110111110";
rowmem(7)<="1111101111000001";
rowmem(8)<="1111001111110010";
rowmem(9)<="1111001111110010";
rowmem(10)<="1111001111110010";
rowmem(11)<="1110101111001010";
rowmem(12)<="1111010001110111";
rowmem(13)<="1111010001110111";
rowmem(14)<="1111001111110010";
rowmem(15)<="1111010001110111";
done<='1';

end if;
end process;
process(clk)
--type zarray is array(0 to 7)of std_logic_vector(15 downto 0);
variable z:array1;

--type warray is array(0 to 7)of std_logic_vector(15 downto 0);
variable w:array2;
variable p:integer:=0;
begin
if(clk='1' and clk'event)then
if (done='1')then
for m in 0 to 15 loop
for n in m+1 to 15 loop
if(node(m)=node)then
z(p):=rowmem(m);
w(p):=rowmem;
p:=p+1;
if(p>7) then
p:=0;
end if;
end if;
end loop;
end loop;
end if;

end if;
we<=z;
pr<=w;
end process;
end Behavioral;

/code

 

[TrickyDicky]

The best way to make it synthesisable is to
1. delete this code.
2. Draw your circuit.
3. Start writing the code to describe your circuit.

The code you have is written too much like software. You cannot write VHDL if you dont know what the circuit should be.

 

[ammassk]

Here I have written the code for getting data's from one memory location using the information from other memory. How can I describe this in circuit level?Please help me.

 

[TrickyDicky]

well you probably need a memory and some sort of counter to access it.