Nov 29, 2007 #1 E EDA_hg81 Advanced Member level 2 Joined Nov 25, 2005 Messages 507 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,298 Activity points 4,808 How to make sure timing is fine in xilinx FPGA moduel design? Thanks.
Nov 29, 2007 #2 I Iouri Advanced Member level 2 Joined Aug 17, 2005 Messages 678 Helped 87 Reputation 174 Reaction score 8 Trophy points 1,298 Activity points 4,814 make sure you constrain every pin on your design(including async, and resets), make sure you identify every false path in yor design, make sure you crossing clock domain correctly make sure read your timing report do post simulation
make sure you constrain every pin on your design(including async, and resets), make sure you identify every false path in yor design, make sure you crossing clock domain correctly make sure read your timing report do post simulation
Nov 29, 2007 #3 E EDA_hg81 Advanced Member level 2 Joined Nov 25, 2005 Messages 507 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,298 Activity points 4,808 Re: How to make sure timing is fine in xilinx FPGA moduel de make sure you crossing clock domain correctly Click to expand... What I should do for crossing clock domain correctly ? A simple example.. Thanks.
Re: How to make sure timing is fine in xilinx FPGA moduel de make sure you crossing clock domain correctly Click to expand... What I should do for crossing clock domain correctly ? A simple example.. Thanks.
Nov 29, 2007 #4 I Iouri Advanced Member level 2 Joined Aug 17, 2005 Messages 678 Helped 87 Reputation 174 Reaction score 8 Trophy points 1,298 Activity points 4,814 use dual clock fifos, use two series flip-flops, when signal from CD going to another
Nov 29, 2007 #5 E EDA_hg81 Advanced Member level 2 Joined Nov 25, 2005 Messages 507 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,298 Activity points 4,808 Re: How to make sure timing is fine in xilinx FPGA moduel de Thank you. Would you let me know any reference materials for those ideas? use two series flip-flops Click to expand... is for canceling metastability ?
Re: How to make sure timing is fine in xilinx FPGA moduel de Thank you. Would you let me know any reference materials for those ideas? use two series flip-flops Click to expand... is for canceling metastability ?
Nov 30, 2007 #6 I Iouri Advanced Member level 2 Joined Aug 17, 2005 Messages 678 Helped 87 Reputation 174 Reaction score 8 Trophy points 1,298 Activity points 4,814 yep Added after 50 seconds: opps sorry for the reference materials it comes from experience PM me and we will discuss
yep Added after 50 seconds: opps sorry for the reference materials it comes from experience PM me and we will discuss
Dec 1, 2007 #7 E EDA_hg81 Advanced Member level 2 Joined Nov 25, 2005 Messages 507 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,298 Activity points 4,808 Re: How to make sure timing is fine in xilinx FPGA moduel de If I get any questions, I am going to bother you more. So much thanks for your help.
Re: How to make sure timing is fine in xilinx FPGA moduel de If I get any questions, I am going to bother you more. So much thanks for your help.