How to make sure timing is fine in xilinx FPGA moduel design

[EDA_hg81]

How to make sure timing is fine in xilinx FPGA moduel design?

Thanks.

 

[Iouri]

make sure you constrain every pin on your design(including async, and resets),
make sure you identify every false path in yor design,
make sure you crossing clock domain correctly
make sure read your timing report
do post simulation

 

[EDA_hg81]

Re: How to make sure timing is fine in xilinx FPGA moduel de

make sure you crossing clock domain correctly

What I should do for crossing clock domain correctly ?

A simple example..

Thanks.

 

[Iouri]

use dual clock fifos,
use two series flip-flops, when signal from CD going to another

 

[EDA_hg81]

Re: How to make sure timing is fine in xilinx FPGA moduel de

Thank you.

Would you let me know any reference materials for those ideas?

use two series flip-flops

is for canceling metastability ?

 

[Iouri]

yep

Added after 50 seconds:

opps sorry for the reference materials it comes from experience PM me and we will discuss

 

[EDA_hg81]

Re: How to make sure timing is fine in xilinx FPGA moduel de

If I get any questions, I am going to bother you more.

So much thanks for your help.