omara007
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ani_edaboard said:If u want to avoid that latency period u can use look-up tables to store the value of Cos or Sines of ur required angles. It is equally feasible in FPGA or ASIC. .
arunragavan said:but omara as long as you have stored inputs in LUTs..you can always work on it..did u try using LUTs? as ani said you can surely reduce the latency..
with regards,
arun
whizkid said:hi omara..
You didnt mention required clock speed for the CORDIC ARCtan calculation..Also the bitwidth of I/Q values..
If your clock speed is less than 20Mhz and your process is 13u or better .. you can do the arctan calculation in one clock cycle with upto 7 classic cordic iterations(assumiing less than 9 bit I/Q inputs)..whizkid
16 bits !! and 8 MHz ..may be within 2-3 clocks u can do arctan with classic algo.The required clock is 8 MHz .. and the process is 13u .. but the I/Q are 16-bits ..
Actually there are 100's of variations of classic cordic algorithm.. many of these variations can be used only in rotation mode. they wont work in vector mode, which is needed for arctan calculation.. the papers i uploaded are the among the very few cordic algos that work for both modes.u mentioned something like the fast algorithm can't work on Vectoring mode .. can u explain more ? ..
whizkid said:16 bits !! and 8 MHz ..may be within 2-3 clocks u can do arctan with classic algo.The required clock is 8 MHz .. and the process is 13u .. but the I/Q are 16-bits ..
well I think the I/Q bitwidth is too much.. what is the expected accuracy of result?
[whizkid
kelvin_bao said:is any body know where use the CORDIC model most?
it seems this algorithm very useful
I use CORDIC rectangular-to-polar conversion in my phased-array beamformer FPGA projects. It converts the complex results to magnitude-phase pairs. I use full pipelining to get one pair of results on each clock cycle.kelvin_bao said:is any body know where use the CORDIC model most?
it seems this algorithm very useful
I didnt say bandwidth is high... I said I/Q bit-width (or sample width) is high..Why do you think the bandwidth is too much ? .. I am desiging a receiver and the sample width is optional
what amazes me is that , how u arrived on this 16 bit sample width(usually selected on basis of required accuracy) ..I took it as 16-bit (can also be 10-bits according to which ADC i will be using) .. and the base-band works on 8 MHz clock .. would you please tell me what amazes u first ?
the simplest cordic explanation i ever found is thisand second, how can I use the classic algos to do it in 2-3 clocks ?!! ..
I also had gone thru opecores cordic core.. i remember it was not so good..by the way .. am currently using the CORDIC core from opencores, which appears to me very primitive as the code is basically written for FPGA and I can't even see an asynchronous reset in the blocks !! ..
hope u understood that i was not reffereing to bandwidth... i am not sure abt bandwidth samplewidth relation... i guess the Rf-signal amplitude variations will be more for higher samplewidth. which inturn may deteriorate the link quality..P.S. What's the relation between the bandwidth and the sample width ????!!!!!!
whizkid said:what amazes me is that , how u arrived on this 16 bit sample width(usually selected on basis of required accuracy) ..
Even in very high speed wireless basebands(say UWB . datarate =480Mbits/sec), the accuracy requirement is not so high..
whizkid
Expenses are Area,Power and pipeline latency etcc.. you can easily see that a 16 bit adder has more delay than an 8bit adder which increases the number of clocks to finish an operation.... moreover as i said earlier 16bits are required only if u intend to do 16 cordic iterations..I have designed 802.11a/b/g systems before and we used 16-bit sample as well .. there are no expenses paid against using 16-bit sample if you want to build a highly accurate system ..
if u have a matlab/spw model u can change the bitwidth and check the charateristics..btw which wpan system u r designing?in case of my current system, it's a short range wireless system .. effectively a WPAN .. and has a ppm that allows a phase shift between TX and RX of as big as 6*Pi angle or even more .. so, the probability of losing a packet is very high if ur SNR is not relatively high .. so , I'm trying my best to raise any probability of catching accurate data .. even if not relavent to ppm problem ..
its a tradeoff.. if u want more acccuracy , u will lose on area and power.. I just enquired my collegue who designed wlan b/g chipset in my company. he said, we used 8bit sample width..anyhow .. i am having everything generic till this moment .. and I can use either 10 or 16 bit sample .. but I don't think i will go for 8 bit ..
whizkid said:if u have a matlab/spw model u can change the bitwidth and check the charateristics..btw which wpan system u r designing?
whizkid
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