How to make a test bench and verify a HDLC-based protocol payload deframer in VHDL?

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adamsogood

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Hi, Guys,

I just finished an HDLC(High-level data link control)-based protocol payload deframer on Xilinx FPGAs. My design is targeted on PCI-express bus. Does anyone suggest me how to make a test bench and verify my design? thank you.
 

hdlc simulator

Your testbench should emulate the existance of the serial interface and the host interface through the PCI Express .. in other worlds, force your test vectors on the bus itself, not on the blocks inputs ..
 

vhdl hdlc

adamsogood said:
Hi, Guys,

I just finished an HDLC(High-level data link control)-based protocol payload deframer on Xilinx FPGAs. My design is targeted on PCI-express bus. Does anyone suggest me how to make a test bench and verify my design? thank you.
Click to expand...

I'm little surprised that you directly went to FPGA without any simulation/testbench. For a HDLC like design, I would highly recommend a more modular testbench ala VMM/AVM etc. Atleast you should start with a task based testbench. You can find some examples of task based tb in opencores designs - though not a great one from a TB standpoint, can help you to some extent. For VMM, my recent book has lot of simple examples, see: www.systemverilog.us and also our SNUG 2006 paper.

Now, if you are looking for a crash course kind of thing, my company offers a "Comprehensive Functional Verification" course in Bangalore, see: www.noveldv.com, contact us at cvc.training <> gmail.com if interested.

Good Luck
Ajeetha, CVC
www.noveldv.com
 

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