How to make a full adder using half-adder module in VHDL?

[kumar_eee]

I am having a Halfadder Module... I want to make a Full adder by using the Halfadder module... How to implemnt it in VHDL?....

 

[Renjith]

half-adder instantiation

hi,
using 2 halfadders u can implement a fulladder.
connect 2 inputs to first halfadder, and connect the 3rd input and the "SUM" output of the first halfadder to the second halfadder. the "SUM" result of the 2nd halfadder will be a fulladder "Sum" output. Use an OR gate to get the "carry" out signal. Connect the "carry" out of the first and second halfadders to that OR gate to get the Full adder "Carry" out.

 

[barkha]

named instantiation vhdl

Using half adder as a component in the full adder

First design the half adder. Using 2 half adders and one OR gate implement
full adder.
=========Half Adder=========================
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY half_adder IS
PORT (A, B : IN std_logic;
Sum, Cout : OUT std_logic);
END half_adder;

ARCHITECTURE myadd OF half_adder IS
BEGIN
Sum <= A xor B;
Cout <= A and B;
END myadd;
====================================

=============Full Adder=========================
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY full_adder IS
PORT (A1, B1, Cin1 : IN std_logic;
Sum, Co1 : OUT std_logic);
END full_adder;

ARCHITECTURE myfulladd OF full_adder IS
signal Sum1,Cout1,Cout2:std_logic;
Component half_adder
port (A,B:in std_logic;
Sum, Coutut std_logic);
end component;

BEGIN
H1:half_adder port map(A1,Cin1,Sum1,Cout1);
H2:half_adder port map(Sum1,B1,Sum,Cout2);
Co1 <= Cout1 or Cout2;
END myfulladd;
======================================================

 

[ikru26]

Re: Instantiation - VHDL using gates

entity FULL_ADDER is

port (

A_IN, B_IN, C_IN : in BIT;

SUM, C_OUT ut BIT);

end FULL_ADDER;



architecture STRUCTURE of FULL_ADDER is

-- Component declarations

component XOR_2

port (

A, B : in BIT;

Z : out BIT);

end component;

component AND_2

port (

A, B : in BIT;

Z : out BIT);

end component;

component OR_2

port (

A, B : in BIT;

Z : out BIT);

end component;

-- Configuration specifications

for all : XOR_2 use entity WORK.XOR_2(ALGORITHM);

for all : AND_2 use entity WORK.AND_2(ALGORITHM);

for O1 : OR_2 use entity WORK.OR_2(ALGORITHM);

-- Signal declarations

signal S1, S2, S3 : BIT;



begin

-- Component Instantiations using named association

X1 : XOR_2 port map (A => A_IN, B => B_IN, Z => S1);

X2 : XOR_2 port map (A => S1, B => C_IN, Z => SUM);

A1 : AND_2 port map (A => S1, B => C_IN, Z => S2);

A2 : AND_2 port map (A => A_IN, B => B_IN, Z => S3);

O1 : OR_2 port map (A => S2, B => S3, Z => C_OUT);