Re: VHDL starter question
Hi,
There are ways to delay a signal in behavioural code using the 'after' reserved word. I guess you are interested in delaying your signal in your RTL, in that case you need a counter.
If you have a 20MHz clock and you want to delay a signal by 10 seconds you need a big counter, doable but big...a 28 bit counter or something like that. If your master clock is slower than that, let's say 1KHz then smaller counter...
I hope it helps
-maestor