How to make a better design for this SMPS post regulator filter circuit?

Akanimo · Feb 8, 2019

FvM said:
The power supply of interest is Traco TML series, and of course current limited. Furthermore, output ripple is specified not to exceed 100 mVpp wideband, so the assumed 1V ripple voltage is just pointless. Low frequency ripple in the 100 Hz range will be probably below 1 mV, and as previously mentioned, you shouldn't expect the SMPS to sink current, the output rectifier can't.

Yes, you're right. With the integrator in the loop, the low frequency disturbances are greatly reduced. High frequency disturbances too.

The OP should concentrate on frequencies around the crossover with noise input not exceeding the specified 100mV. Obviously, the SMPS model needs improvement.

Knowing the converter topology could give a direction on where the crossover frequency might be.

doncarlosalbatros · Feb 14, 2019

Dear all,

Here is my final version:

I also attached a rar file where I put the asc file for you to run if you use LTspice.

These mortification came after I read this document.

I used this diagram except with a different LDO.

Let me know if you have any input to this filter. I have added the asc file if you would like to simulate or modify.

Thanks

How to make a better design for this SMPS post regulator filter circuit?

Akanimo

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doncarlosalbatros

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How to make a better design for this SMPS post regulator filter circuit?

Akanimo

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