library IEEE;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
.....
signal stage1 : unsigned (63 downto 0);
signal stage2 : unsigned (39 downto 0);
...
[COLOR="#FF0000"]stage2(4 downto 0) <= stage1(7 downto 4) + stage1(3 downto 0) ;[/COLOR]
after synthesis , there is error : " Target slice is 5 elements ; value is 4 elements ". Then i change inputs to 5 elements, but the timing is increase.
in verilog 4 bits + 4 bits => 5 bits is OK, how to do that in VHDL?
a(4) is a std_logic type. It is not an array. There are no arithmetic functions for std_logic type.
a(4 downto 4) is an unsigned type of length 1. hence you can do arithmatic on it.
a(4) is a std_logic type. It is not an array. There are no arithmetic functions for std_logic type.
a(4 downto 4) is an unsigned type of length 1. hence you can do arithmatic on it.