Oct 26, 2012 #1 vimalraj205 Member level 3 Joined Oct 11, 2011 Messages 65 Helped 16 Reputation 32 Reaction score 14 Trophy points 1,288 Activity points 1,670 hai friends i am a newbie to use primetime for timing analysis ...... i have my verilog , library files and sdc file how to load these into primetime i went in this order read_verilog read_lib read_sdc but when i give report_timing it says there is no constraints can anybody please help me to work on it thank you in advance
hai friends i am a newbie to use primetime for timing analysis ...... i have my verilog , library files and sdc file how to load these into primetime i went in this order read_verilog read_lib read_sdc but when i give report_timing it says there is no constraints can anybody please help me to work on it thank you in advance
Oct 27, 2012 #2 S soloktanjung Full Member level 6 Joined Nov 20, 2006 Messages 364 Helped 51 Reputation 100 Reaction score 43 Trophy points 1,308 Location nowhere Activity points 3,194 If the tool complain that there is no constraints, so check you constraint file and make sure you constraint your design. That's all. Thanks.
If the tool complain that there is no constraints, so check you constraint file and make sure you constraint your design. That's all. Thanks.
Oct 28, 2012 #3 S sakthikumaran87 Full Member level 3 Joined Nov 9, 2009 Messages 160 Helped 21 Reputation 42 Reaction score 21 Trophy points 1,298 Location India Activity points 2,176 hei b4 that is it possible to do STA on verilog files? You should synthesis it and input the netlist to primetime which can be in *.v format. But not RTL files directly. Correct me if wrong.
hei b4 that is it possible to do STA on verilog files? You should synthesis it and input the netlist to primetime which can be in *.v format. But not RTL files directly. Correct me if wrong.