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How to layout the mos capacitor to decrease the leakage I ?

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xihuwang

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Hi, every one :
I am working on a pll project. The LPF capacitor needed is 50pF. The only
capacitor I can use is mos capacitor.
I have below questions want to ask :
1. If the TOX = 7nm ( 0.35 um process) , how much is the leakage current
for a 50 pF nmos capacitor ( Gate as anode, D S B short to gnd)
2. What is the main cause of current leakage
3. What's the mos capacitor structure should I take to decrease the leakage.
4. Some one tell me , maybe the bird break is the main reason for leakage,
If so , what should I do?
 

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