How to know that our setup and hold time are violated?

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pradeep2323

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how can we come to know that our setup time or hold time violated???
 

Re: setup and hold time

seeing the timing report which is generated by the tool
 

setup and hold time

Constrain your design ( e.g. create clocks on all external/internal clock sources) and look at timing reports...
 

Re: setup and hold time

you can identify the setup- and hold-time violations in both static and dynamic timing analysis.
 

setup and hold time

at what stage of design u r checking?
 

setup and hold time

u can generate reports for timing violations
 

Re: setup and hold time

Both in FPGA and ASIC, you can read the timing report, if the path slack is plus, then the setup is met.
 

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