Apr 19, 2007 #1 P pradeep2323 Junior Member level 3 Joined Nov 2, 2006 Messages 27 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,487 how can we come to know that our setup time or hold time violated???
Apr 19, 2007 #2 X xstal Full Member level 2 Joined Oct 12, 2006 Messages 138 Helped 20 Reputation 40 Reaction score 0 Trophy points 1,296 Location USA Activity points 2,197 Re: setup and hold time seeing the timing report which is generated by the tool
Apr 19, 2007 #3 R rjainv Full Member level 2 Joined Feb 18, 2007 Messages 138 Helped 18 Reputation 36 Reaction score 4 Trophy points 1,298 Location Bangalore, India Activity points 2,066 setup and hold time Constrain your design ( e.g. create clocks on all external/internal clock sources) and look at timing reports...
setup and hold time Constrain your design ( e.g. create clocks on all external/internal clock sources) and look at timing reports...
Apr 19, 2007 #4 Y yjkwon57 Full Member level 4 Joined Jul 31, 2004 Messages 218 Helped 24 Reputation 48 Reaction score 3 Trophy points 1,298 Activity points 1,808 Re: setup and hold time you can identify the setup- and hold-time violations in both static and dynamic timing analysis.
Re: setup and hold time you can identify the setup- and hold-time violations in both static and dynamic timing analysis.
Apr 20, 2007 #5 S shiv_emf Advanced Member level 2 Joined Aug 31, 2005 Messages 605 Helped 22 Reputation 44 Reaction score 6 Trophy points 1,298 Activity points 4,106 setup and hold time at what stage of design u r checking?
Apr 25, 2007 #6 T thamarai Member level 1 Joined Mar 9, 2007 Messages 32 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,404 setup and hold time u can generate reports for timing violations
Apr 25, 2007 #7 Q quan228228 Full Member level 4 Joined Mar 23, 2006 Messages 196 Helped 16 Reputation 32 Reaction score 3 Trophy points 1,298 Activity points 2,571 Re: setup and hold time Both in FPGA and ASIC, you can read the timing report, if the path slack is plus, then the setup is met.
Re: setup and hold time Both in FPGA and ASIC, you can read the timing report, if the path slack is plus, then the setup is met.