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How to isolate substrate noise in mixed signal chip

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Jim_Fu

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Dear all,

In mixed signal chip, the huge digital block and I/O buffer noise will affect analog circuit performance through substrate,if put the analog block above Deep Nwell will reduce the effect,but some device PNP,Native Transistor are not allowed above Deep Nwell;so I want to put the digital block and I/O circuit above Deep Nwel,but I worry about I/O circuit above Deep Nwell will lead to ESD issue,anyone can give me some suggestion?

Thanks in advance,

Jim
 

protonixs

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Jim_Fu said:
Dear all,

In mixed signal chip, the huge digital block and I/O buffer noise will affect analog circuit performance through substrate,if put the analog block above Deep Nwell will reduce the effect,but some device PNP,Native Transistor are not allowed above Deep Nwell;so I want to put the digital block and I/O circuit above Deep Nwel,but I worry about I/O circuit above Deep Nwell will lead to ESD issue,anyone can give me some suggestion?

Thanks in advance,

Jim

Jim,

separate the power supply of the analog blocks from the digital ones;they should only be connected at the pad...
if possible, put double-guardring to all blocks...
please refer to the image below in making a double-guardring.
the purple one is Nwell and inside of it is n+ active. connect it to VDD.
the outer guard ring is p+active; it must be connected to VSS/grnd.

i hope this helps...

regards

 

iexplorer

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How about a block with both analog and digital part ,such as S/H in ADC, digital signal control the analog signal pass?
 

protonixs

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iexplorer said:
How about a block with both analog and digital part ,such as S/H in ADC, digital signal control the analog signal pass?
hi!
that is an special case if it can not really be avoided.
try rearranging the devices until no digital lines passes through analog signal.
if it is not possible, put some dummy p+ active to both sides of the digital lines to couple some noise to the ground; remember to connect this active to ground.

if the digital passes through the diff input, be sure to pass it trough both the diff inputs to cancel whatever noise is present out.
 

leo_o2

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I can't understand "I/O circuit above Deep Nwell will lead to ESD issue". Anyone can explain to me.
In my opinion, ESD is OK for that.
 

forkschgrad

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why is it that the one with the p+ active/sub is the outermost. and the ones with the n+ active is inner?
 

protonixs

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forkschgrad said:
why is it that the one with the p+ active/sub is the outermost. and the ones with the n+ active is inner?
hello forkschgrad!
i made a mistake in my statement... VDD/n+actvive should be the one in the outermost part to isolate the noise...
thanks for asking...
regards
 

jcpu

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Hello Jim_fu,

you might want to take a look at literatures by
allstot or van der plus, both ieee fellows i believe.

Have fun,
 

forkschgrad

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i had an experience wherein after placing the p+ and the n+, another p+ was placed. what for?
 

protonixs

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forkschgrad said:
i had an experience wherein after placing the p+ and the n+, another p+ was placed. what for?

i think the purpose of that is to strengthen the connection between psub and Ground/VSS; but this technique has some drawbacks. one effect is it increases the possibility of noise from digital blocks to interfere the analog blocks.
 

tia_design

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What I did for my current chip is to seperate analog and digital part, put thicker guard ring between them, also put guard ring around those high frequency block.
 

layout_designer

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I think the guard rings are used for absorbing stray electrons and holes ( which are equivalent to noise) as well as to take care of latchup.

Use separate IOs for digital and analog power supplies. Use sperate power supplies for IOs.

Added after 2 minutes:

In addition, some decoupling caps are placed between digital and analog blocks.
 

forkschgrad

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protonixs said:
forkschgrad said:
i had an experience wherein after placing the p+ and the n+, another p+ was placed. what for?

i think the purpose of that is to strengthen the connection between psub and Ground/VSS; but this technique has some drawbacks. one effect is it increases the possibility of noise from digital blocks to interfere the analog blocks.

how is it affected? the extra p+ was placed between MOS and bipolar xsistors.
 

joe_chen

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Deep Nwell not include ESD

What is the reason for that?
 

she_long

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I think the p+ guardring of the double guardring is to absorb the noise from substrate, the n+ (connected to nwell) is to prevent the substrate noise, am I right.
 

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