How to invoke dc and prime time

[limitless_21]

Hi,

I am working on RC (RTL Compiler) for last 3 years and now i have to use DC (Design Compiler) for synthesis.
I also have to Timing analysis using Prime time.

I am having issues in invoking both the tools.
Please do let me know how to invoke both the tools and the environment settings which are required to setup before we invoke them.

Thanks
limitless

 

[rca]

dc_shell
pt_shell

 

[kck_246023]

dc_shell
invoke DC from work directory which should contain .dc.setup<file>
maintain directory structure for DC
like
DC is main directory
in this sub-dir
work
source- (.v/.vhd)
ref(libraries)
scripts
netlist
reports

 

[limitless_21]

HEy thanks a lot rca and kck_246023, but i am getting the error when i am trying to invoke dc
I am giving theoptions -dcsh_mode, -db_mode and independently i also gave -tcl_mode, but the errror is showing as

Fatal: Design Compiler is not enabled [DCSH-1]

Please give a quick reply as to what has to be done here

 

[rca]

from solnet synopsys website:

DCSH-1
NAME
DCSH-1 (fatal) %s is not enabled. 

DESCRIPTION
You don't have the given license available. 

WHAT NEXT
Check and get the desired license by invoke the get_license command. 


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