suhas007
Newbie level 5
for eg i hav
entity abc is
port(a:in std_logic;
b
end abc;
architecture
component def
port(a:in std_logic;
b
end def;
begin
uut:def portmap(a=>,
b=>b);
end
Now if i want to intialize a to '1' then how to do that in portmap statement
entity abc is
port(a:in std_logic;
b
end abc;
architecture
component def
port(a:in std_logic;
b
end def;
begin
uut:def portmap(a=>,
b=>b);
end
Now if i want to intialize a to '1' then how to do that in portmap statement