[SOLVED] How to intialize a signal in portmap

[suhas007]

for eg i hav
entity abc is
port(a:in std_logic;
but std_logic);
end abc;

architecture
component def
port(a:in std_logic;
but std_logic);
end def;

begin
uut:def portmap(a=>,
b=>b);
end


Now if i want to intialize a to '1' then how to do that in portmap statement

 

[std_match]

a => '1'

 

[TrickyDicky]

do you mean initialise or connect it to?
Initialisation is done at start up and is usually done on a signal that can transition.
Connecting a to '1' means it is driving '1' and will always be '1'.