Re: ad &fpga
Dear asmer,
If you have to stay with your FPGA and have no other alternative, then you need to start thinking about a way to slow down the flow of data.
One quick idea, it to find a high speed FIFO, with 1GHz, it will be really difficult, but if you find a FIFO that has the possibility to change the data width of the information. According to the datasheet for the component, the output of the ADC is 16 bits LVDS at max 500 MHz. By putting a 16/32 FIFO between the ADC and your FPGA, your datarate will go down to 250 MHz. It maybe OK for your FPGA to handle, but I would really look for something else if I was you.
Todays FPGAs can handle up to 650MHz datarate, I would deffinitely go for a faster FPGA, then you connect the FPGA pins to the output of the ADC directly, it will be a much cleaner design with the minimum amount of components on that board.
There are other way to slve this, depending on what you want to do with the captured data, 1G Bytes of information is a hell of a lot and you need a really big FPGA or a gigantic memory of you want to do any signal processing on it. And big FPGAs today, can handle really high speed LVDS signals and 500MHz data rate will not be a big problem for them.
Good luck with your design,
/Farhad