The PROM goes to the FPGA alone. The CPLD doesn't need PROM, and is programmed via JTAG, on it on-board non-volatile RAM (flash). There's no special arrangement imposed to the chips layout, but on the programming side, you should just daisy-chain the JTAG chain.
That is, you link together all the TMS, TCK and TRST, and from the programming JTAG header, you go from the header pin named TDI to the first chip TDI, then, from that chip TDO to the next chip TDI, then from that TDO to the last chip TDI, and from that last chip TDO back to the JTAG header pin labled TDO.
In the chain, you can put any chip first, but usually, since the PROM and FPGA are related, it would be logical to chain them next to each other.