How to interconnect, in a single net different, signals of different instantiations?

[rmmy]

Is it possible in Verilog/System Verilog to inetrconnect with a single net different signals of (different vector widths) of different instantiations?
when I tried this code in ModelSim I dont get any compilation error. But with VCS I am getting compilations error. I want to know if it is allowed?

the error with VCS simulator I get is:

7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}

7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}


Sample Code is as follows:
module top (
input/output declarations
);

wire clk;

cksysinthspinetbr icksysinthspinebrp (
.ckuclksysintgdtbl ({4{clk}}),//"ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),//"ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15b[20:11] ),
.pguclks16tbr(pguclks16tbr),
.pguclks17mtbr(pguclks17mtbr)
);

//------------------------

cksysinthspinetbr icksysinthspinetrp (
.ckuclksysintgdtbl ({4{clk}}),// "ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),// "ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15t[20:11] ),
.pguclks16tbr(pguclks16tbl),
.pguclks17mtbr(pguclks17mtbl)
);

endmodule

 

[tkkg3000]

Re: Verilog

Is it possible in Verilog/System Verilog to inetrconnect with a single net different signals of (different vector widths) of different instantiations?
when I tried this code in ModelSim I dont get any compilation error. But with VCS I am getting compilations error. I want to know if it is allowed?

the error with VCS simulator I get is:

7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}

7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}


Sample Code is as follows:
module top (
input/output declarations
);

wire clk;

cksysinthspinetbr icksysinthspinebrp (
.ckuclksysintgdtbl ({4{clk}}),//"ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),//"ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15b[20:11] ),
.pguclks16tbr(pguclks16tbr),
.pguclks17mtbr(pguclks17mtbr)
);

//------------------------

cksysinthspinetbr icksysinthspinetrp (
.ckuclksysintgdtbl ({4{clk}}),// "ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),// "ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15t[20:11] ),
.pguclks16tbr(pguclks16tbl),
.pguclks17mtbr(pguclks17mtbl)
);

endmodule

Hi rmmy,

Your question is interesting.I have little knowledge about Verilog, but I would like to discuss with you about this matter.

I think it is legal when we use the same signal for different modules.
However,is it legal when we use connection like that:

.ckuclksysintgdtbl ({4{clk}}) ? While we declared that:
wire clk; //only 1-bit width.

I think that the mistake occurred when you used above connection.

Could you declare that:

wire [3:0] clk; ?

And you do the above connection again (please comment out the .ckuclksysintgdtbr ({90{clk}}) connection).

Please inform me the result.I also want to know the result.

 

[ljxpjpjljx]

Re: Verilog

different simulator will behave differently!

 

[tkkg3000]

Re: Verilog

different simulator will behave differently!

Your answer may be right. For instance,you can simulate a sample RTL by using NC-Verilog or VCS.The result will have some differences,especially, in racing conditions.
But I think it will be better if we write RTL code clearly.We won't encounter to the difficult situation.Especially,in case the RTL is synthesized.
Anyway,I am waiting for the result from rmmy.If it still has problem,my suggestion can not be applied.

 

[FvM]

Verilog

To my opinion, the error message is very clear and understandable:

multi-concat cannot be used on the high-conn
of a inout or out port

It clarifies a point that you forget to mention: ckuclksysintgdtbl is apparently a 4-bit-wide output signal. You're trying to drive a bit signal (clk) from a four bit signal respectively from four sources. That can't work, with no simulator or synthesis tool. The problem hasn't anything to do with module instantiations, it's a simple multiple-source error, that's the whole story.

 

[tkkg3000]

Re: Verilog

ckuclksysintgdtbl is apparently a 4-bit-wide output signal. You're trying to drive a bit signal (clk) from a four bit signal respectively from four sources.

Thanks FvM for your answer.

However,I want to confirm my understanding:
1. The error doesn't occur if we declare that:

wire [3:0] clk;

We do the connection again( the 90{clk} is commented out from 2 modules,of course).
2.The connection 4{clk} is illegal,because clk is only 1-bit width.

Please correct me if my understanding is wrong.

 

[FvM]

Verilog

wire [3:0] clk can solve the multiple-source problem. But I can't suggest how to connect the two modules, cause I don't know what's the purpose of the clk vectorial signal.

 

[tkkg3000]

Re: Verilog

Hi FvM,
Thank you for your answer.