[SOLVED] How to instruct DC to correctly check the timing of a two-edges design?

[irun2]

I have a design that has to used both rising and falling edges of a clock, to improve the holdtime margin. But I found DC has problem when doing timing analyze.
The hold time report looks like below. The clock period is 20ns, and I think the correct hold time slack should be 10ns+0.108= 10.108ns.

  Startpoint: wdata_i[0]
              (input port)
  Endpoint: mctl/iram
            (rising edge-triggered flip-flop clocked by cpu_clk')
  Path Group: cpu_clk
  Path Type: min

  Point                        Fanout     Trans      Incr       Path
  ---------------------------------------------------------------------
  clock (input port clock) (rise edge)              0.000      0.000
  clock network delay (ideal)                       0.000      0.000
  input external delay                              0.000      0.000 r
  wdata_i[0] (in)                         0.000     0.000      0.000 r
  wdata_i[0] (net)               1                  0.000      0.000 r
  U38/Y (AOI22X1)                         0.096     0.059      0.059 f
  n29 (net)                      1                  0.000      0.059 f
  U37/Y (INVX1)                           0.054     0.049      0.108 r
  iram_wdata_v[0] (net)          1                  0.000      0.108 r
  mctl/din_i[0] (cpu_iram)                          0.000      0.108 r
  mctl/din_i[0] (net)                               0.000      0.108 r
  mctl/iram/D[0] (sram_8kx8)              0.107     0.000      0.108 r
  data arrival time                                            0.108

  clock cpu_clk' (rise edge)                       10.000     10.000
  clock network delay (ideal)                       0.000     10.000
  mctl/iram/CLK (sram_8kx8)                         0.000     10.000 r
  library hold time                                 0.000     10.000
  data required time                                          10.000
  ---------------------------------------------------------------------
  data required time                                          10.000
  data arrival time                                           -0.108
  ---------------------------------------------------------------------
  slack (VIOLATED)                                            -9.892

 

[matter]

The hold time report looks correct to me. I am not sure why you think it should be 10.108.

If your intention was to time at different edges, then you should use appropriate constraints to tell the tool to do so. Otherwise the default behaviour of the tool is to time the worst possible edges.

 

[irun2]

Hi matter,
But I think DC has got the wrong hold relationship, It should not check the hold on 0ns of the launch edge, it should have been check the next rising edge, that is 20ns.
20+0.108-10=10.108.
The question is how can I put constaints to let DC check the correct hold relationship?

 

[matter]

You can use set_multi_cycle_path -hold constraint.

Regards

 

[irun2]

You can use set_multi_cycle_path -hold constraint.

Regards

Thanks a lot, I'll give it a try