# How to instantiate SystemVerilog netlist inside Verilog-2001

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#### jwdonal

##### Newbie level 5
I need to make the subject line a bit more specific:

"How to instantiate a SystemVerilog netlist (with an interface at the top-level) inside of a Verilog-2001 module".

I have an SV design that has an interface at the top-level as follows:

Code:
module my_design_top (

//more ports...
Video_Output_If.mp_drvr vid_out_if,
//more ports...

);

// code here

endmodule

The interface definition is as follows:

Code:
interface Video_Output_If ();

logic o_vid_de;
logic o_vid_hsync_n;
logic o_vid_vsync_n;

modport mp_drvr (
output o_vid_de,
output o_vid_hsync_n,
output o_vid_vsync_n
);

endinterface : Video_Output_If

So my question is, once I synthesize this design, how do I then instantiate it in a verilog-2001 module? It must be possible right?? (I hope.) But I can't seem to figure it out. I've tried the following:

Code:
my_design_top my_design_top_inst (
// other ports

.vid_out_if.o_vid_de(o_vid_de),
.vid_out_if.o_vid_hsync_n(o_vid_hsync_n),
.vid_out_if.o_vid_vsync_n(o_vid_vsync_n),

// other ports
);

But that of course doesn't work because the verilog compiler freaks out about the extra '.' saying:

Error: line 837: unexpected token: '.'

So then I thought I should be able to add a '\' to escape the extra '.' like this:

Code:
.vid_out_if\.o_vid_de(o_vid_de),

But I still got the exact same error about unexpected token. Then I thought that my SV synthesis tool (I'm using Synplify C-2009.06-SP1) would have an option to rename the top-level interface ports into a syntax that would be accessible by Verilog-2001. But I couldn't find any such option - although I don't really know what I'm looking for either. Haha.

Just out of curiosity I opened up the Synplify EDIF netlist and saw the following:

Code:
           (port (rename vid_out_if_o_vid_de "vid_out_if.o_vid_de") (direction OUTPUT)
(property unqual_imvar_name (string "o_vid_de"))
(property svint_from_interface (integer 1))
)
(port (rename vid_out_if_o_vid_hsync_n "vid_out_if.o_vid_hsync_n") (direction OUTPUT)
(property unqual_imvar_name (string "o_vid_hsync_n"))
(property svint_from_interface (integer 1))
)
(port (rename vid_out_if_o_vid_vsync_n "vid_out_if.o_vid_vsync_n") (direction OUTPUT)
(property unqual_imvar_name (string "o_vid_vsync_n"))
(property svint_from_interface (integer 1))
)

I honestly don't know very much about how netlists work but it seems to me that if I could get Synplify to stop "renaming" the '_' back to a '.' then I would have my solution. What do you think?

Any advice you have would be _really_ sppreciated.

Thanks!!

Added after 1 hours 46 minutes:

Well, just out of curiosity I attempted to replace the extra '.' with an underscore in the EDF netlist that I showed you in my previous post and IT WORKED! Can you believe it!? I got my design to implement all the way through to bitstream no problem. Haha.

Here is the modified netlist excerpt (I only changed 3 characters - haha. Notice the extra period is now an underscore for the 'rename' command):

Code:
           (port (rename vid_out_if_o_vid_de "vid_out_if_o_vid_de") (direction OUTPUT)
(property unqual_imvar_name (string "o_vid_de"))
(property svint_from_interface (integer 1))
)
(port (rename vid_out_if_o_vid_hsync_n "vid_out_if_o_vid_hsync_n") (direction OUTPUT)
(property unqual_imvar_name (string "o_vid_hsync_n"))
(property svint_from_interface (integer 1))
)
(port (rename vid_out_if_o_vid_vsync_n "vid_out_if_o_vid_vsync_n") (direction OUTPUT)
(property unqual_imvar_name (string "o_vid_vsync_n"))
(property svint_from_interface (integer 1))
)

Of course, the fact that I have to modify the raw netlist is absolutely silly and a pain to have to do every time I re-synthesize my design. But, hey, at least there is a work-around!

Does ANYONE know of a way to tell Synplify to use this type of naming convention for top-level ports? There must be some Synplify guru out there who has an answer.

Thanks!

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