How to insert two signal nets at APR phase.

[ganapathiraju16]

Hello, How can I insert two signal nets, which should carry a different volage than the rest of the chip, in the design at the APR phase? I want to insert nets such that they just transfer the input to the output port. This means I need two new input ports and two new output ports that are directly connected to each other.

I know I can do it to the design file and synthesize it again, but I need to be done at the APR phase only.

 

[ThisIsNotSam]

I am not sure I understand the need for this, sounds like a hack.

That being said, look into the ECO flow. It can perform changes to the netlist during place and route.