Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
i have a question for all u guyz.in syntheis how can i insert a driving buffer in a critical path to reduce load or fanout on the net .can it be done in logic synthesis ot it can only be done in physical design.plz answer
You can insert buffers in critical path at RTL level also.
For that you need to have the data sheet of the technology library which ur using during synthesis. Based on the timing, fanout parameters u can choose buffers and instation them in the critical path.
But in Synopsys DC u can specfiy the critical path optimization also, it will automatically places the buffer in that path based on the timing and fanout constraints.
Hope this is usefull for, if u have any questions u can ask.
Thanks and regards
I don't have idea on RTL compiler, In DC I insert buffers at RTL as well as netlist level. It doesn't makes much differance, In think it should be same with RTL compiler also. Becoz the interpretation of the code will be same in the both cases.
i have a question.i have done gate level simulation on my netlist.i have synthesized my design for 100mhz freq.it has been done without any violations.but wen i do post synthesis simulation ,my design was not working for 100mhz.some modules were not able to produce the outputs.it is working at 25 mhz only.wat does it mean.wat should i do?