How to insert a driving buffer in a critical path in synthesis?

[nikhilindia85]

i have a question for all u guyz.in syntheis how can i insert a driving buffer in a critical path to reduce load or fanout on the net .can it be done in logic synthesis ot it can only be done in physical design.plz answer

 

[thuyet]

synthesis

Dear friend
As I know.Synthesis just convert your RTL code to Gate level. And how to place and route,insert buffer to all IO,static time.... are belong to Back end design(physical design)
Best regard

 

[nikhilindia85]

synthesis

how to do it in backend

 

[Wenf.Yeh]

synthesis

use Encounter,read the UG

 

[sekapr]

Re: synthesis

both

 

[satyakumar]

Re: synthesis

Hi nikhil,
You can insert buffers in critical path at RTL level also.
For that you need to have the data sheet of the technology library which ur using during synthesis. Based on the timing, fanout parameters u can choose buffers and instation them in the critical path.

But in Synopsys DC u can specfiy the critical path optimization also, it will automatically places the buffer in that path based on the timing and fanout constraints.

Hope this is usefull for, if u have any questions u can ask.
Thanks and regards
satyakumar

 

[vjm16]

Re: synthesis

Thanks satya. The info is helpful for me too.

 

[nikhilindia85]

synthesis

@satya
i am using cadence RTL compiler for synthesis.how can i insert buffers.i have technology lib datasheet.do i need to insert in netlist or is there any command available for that

 

[satyakumar]

Re: synthesis

Hi Nikhil,
I don't have idea on RTL compiler, In DC I insert buffers at RTL as well as netlist level. It doesn't makes much differance, In think it should be same with RTL compiler also. Becoz the interpretation of the code will be same in the both cases.

Thanks and Regards
satyakumar

 

[nikhilindia85]

synthesis

can u tell me how do u that in DC plz.i would like to know.plz elaborate on this

 

[nikhilindia85]

synthesis

i have a question.i have done gate level simulation on my netlist.i have synthesized my design for 100mhz freq.it has been done without any violations.but wen i do post synthesis simulation ,my design was not working for 100mhz.some modules were not able to produce the outputs.it is working at 25 mhz only.wat does it mean.wat should i do?

 

[Thinkie]

synthesis

If your synthesis tool didn't put a buffer... either you don't need it or your constraints are wrong.

Anyway, you can write a simple script that inserts a buffer in particular net if you want to.