How to initialize RAM in Verilog?

Error (276000): Cannot synthesize initialized RAM logic "ram:my_ram|mem"

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initial
begin

$readmemh("init.dat",mem);


end

FvM said:

$readmem is said to be supported by Quartus. I guess there's something special with your design.

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module ram(

address , // Address input
q    , // Data output
qin	,// Data input
we		//write enable
);
input [15:0] address;
output wire [7:0] q; 
input [7:0] qin;
input we;
           
reg [7:0] mem [0:255] ;  
//reg [7:0] q;    
reg [7:0] data_out;


  //$readmemb("memory.list", mem); // memory_list is memory file
  
  
  
  assign q = (!we) ? data_out:8'bz;
  
  
  always @ (  address or we)
begin
if (we)
begin
mem[address] = qin;
end
else 
begin
data_out = mem[address];
end

  
end

initial
begin

$readmemh("init.dat",mem);


end
endmodule

FvM said:

The error message is misleading. Your design doesn't infer block RAM with or without $readmem() because it's not a synchronous RAM description. You need something like this:

Code:

module ram(

address , // Address input
clk,
q    , // Data output
qin	,// Data input
we		//write enable
);
input [15:0] address;
output wire [7:0] q; 
input [7:0] qin;
input we;
input clk;
           
reg [7:0] mem [0:255] ;  
reg [7:0] data_out;

assign q = (!we) ? data_out:8'bz;
  
always @ (posedge clk)
begin
  if (we)
  begin
    mem[address] = qin;
  end
  data_out = mem[address];
end

initial
begin
  $readmemh("init.dat",mem);
end
endmodule

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