How to initialize a union in Systemverilog?

boardlanguage · Apr 10, 2007

I've tried to initialize a union (in Modelsim 6.2f SE) , but it's not working.
I want the union to initialize to '0' (instead of 'X'.) I can't use a 2-state base-type (bit), because the union must be capable of capturing 4-state ('X') values.

Code:

typedef union packed {
  logic blah7;
  logic blah6;
  logic blah5;
  logic blah4;
} t_myunion;

t_myunion foo = { default:0 };

/*
COMPILER ERROR: Illegal assignment of structural literals to union
*/

Is there a way to initialize a union?[/code]

sumit_techkgp · Apr 12, 2007

Ya. Create it and initialize it in a procedural statement
Sumit

modelsim62c · Apr 15, 2007

Yes, you have two choices:
(a) initialize in procedural code (task/subprogram or other program block)
(b) since you declared the struct/union 'packed', you can simply assign it directly to a 4-state literal value -- no need for the braces {}.

Code:

typedef union packed {
  logic blah7;
  logic blah6;
  logic blah5;
  logic blah4;
} t_myunion;

t_myunion foo = 'h42;// single value, only works for packed union/struct

...so you almost had it right the first time

How to initialize a union in Systemverilog?

boardlanguage

Full Member level 1

sumit_techkgp

Full Member level 2

boardlanguage

modelsim62c

Member level 2

boardlanguage

Similar threads

How to initialize a union in Systemverilog?

boardlanguage

Full Member level 1

sumit_techkgp

Full Member level 2

modelsim62c

Member level 2

Similar threads

Privacy & Transparency

Privacy & Transparency