Dec 30, 2007 #1 B balasub Member level 1 Joined May 15, 2007 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,503 verilog tasks -------------------------------------------------------------------------------- hi, i have a verilog file containing the various tasks.... How do i include this file to use the various tasks in my testbench.. this file also has tasks which are dependent on the state of a signal inside the BFM.
verilog tasks -------------------------------------------------------------------------------- hi, i have a verilog file containing the various tasks.... How do i include this file to use the various tasks in my testbench.. this file also has tasks which are dependent on the state of a signal inside the BFM.
Dec 31, 2007 #2 D deepu_s_s Full Member level 5 Joined Mar 24, 2007 Messages 305 Helped 15 Reputation 30 Reaction score 5 Trophy points 1,298 Activity points 3,021 verilog tasks how about 'include ? i think this works
Jan 2, 2008 #3 V venkatesankalidass Junior Member level 3 Joined Jun 14, 2007 Messages 30 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 1,469 Re: verilog tasks `include "full\path\name.v" like the above example use ur design to include task note all the task present iiside the module
Re: verilog tasks `include "full\path\name.v" like the above example use ur design to include task note all the task present iiside the module
Jan 11, 2008 #4 S satishkumar Member level 4 Joined Apr 2, 2006 Messages 70 Helped 2 Reputation 4 Reaction score 0 Trophy points 1,286 Location Bangalore Activity points 1,584 verilog tasks hi send some more detail data regarding task `include
Jan 11, 2008 #5 K kelvin_sg Advanced Member level 4 Joined Aug 17, 2004 Messages 102 Helped 3 Reputation 6 Reaction score 3 Trophy points 1,298 Location Singapore Activity points 852 verilog tasks venkatesankalidass wrote that. it's the exact trick in Verilog I like most. with `include one can write 10k lines of codes in single module without tiring out scrolling ultraedit.. i dream vhdl has that too.
verilog tasks venkatesankalidass wrote that. it's the exact trick in Verilog I like most. with `include one can write 10k lines of codes in single module without tiring out scrolling ultraedit.. i dream vhdl has that too.