how to improve the pll performance

[Haward Zhu]

hi guys, i'm design a clock generator with a 25MHz crystalloid and a 200MHz signal output. i chose the classical pll configuration consisting of PFD CP LF VCO and divider.
i'm in trouble on how to eliminate the static phase error which should not exit in theory. i have no idea if it causes the ripple of the output voltage of CP, and it400ps Jcc.
and i have a question about the pnoise simulation. what does "output frequency sweep range" mean? i chose 10K-800M for the 200MHz output, and i got 400ps Jcc. if i reduce the range(e.g. 150M-300M), results get better. is that valid？how much sweep range i need at least？
thanks！

 

[tony_lth]

It seems that your PLL don't Lock. There are many reasons that can cause bad pll performance. Could you pls paste your circuits and simulation to analysis?

 

[magicfire]

I think the jitter you've got is the vco jitter. and in a pll, the noise of vco in low freq can be filtered by the loop bandwidth,and the noise in high freq should be much small. So the invaid freq should start from the pll f-3db, and the maxium should be less much less than the freq of osc .
you may choose the minium freq lower.