How to improve PSRR of LDO design ?

[mitgrace]

Dear All :
Does anyone have any experience of high PSRR of LDO design ? Any comments or reference document ? Thanks

 

[ram_kumar_abc]

the error amplifier as well as the pass transistor must have very high gain
Only then the psrr will be high. Try increasing the gain of the error amplifier as much as possible..

Added after 1 minutes:

a minimum of 60dB is required from both the stages for getting a high psrr

 

[saro_k_82]

You can supply the error amplifier from the LDO output. The PSRR will be much higher in that case. But this circuit would require startup (which can be avoided as well).

 

[test_123]

You can supply the error amplifier from the LDO output. The PSRR will be much higher in that case. But this circuit would require startup (which can be avoided as well).

interesting idea, may you explain it in detail? why it need startup, how to avoid? thanks!

 

[saro_k_82]

The low supply rejection of the error amplifier contributes most to the supply induced disturbance of the LDO (If the bias current you get is clean., that is).
If you supply the error amplifier from the output of the LDO, which is free from the supply noise to a good extent, the output of the error amplifier's dependence on the supply voltage is further weakened.

The attached figure presents a simplistic view of this.

It needs startup because, at zero state (no currents), there is nothing pushing the amp to work. There has to be some voltage at the output of the LDO to make the error amp work linearly.
The diode connected transistor can be replaced by a resistor as well.
If the last stage of the amp is designed as a folded cascode stage, you would not require a startup circuit.

This would make the LDO PSRR high, but then the output's supply dependence will be limited by the PSRR of the input bias current. You would then need a similar technique at the bandgap block to get to the desired spec.

 

[zizzbear]

Hi saro_k_82,

Is your this LDO working when the output current is 0 ?

In this topology, it seems the Power PMOS can not turn off when no output load current.

I haved tried a similar one, and met the problem, then I change to other topology....

it will be good news to hear if you don´t have this problem ! Then it can be improved !

Thank you very much !

 

[saro_k_82]

Yes I have done it and obtained 120dB PSRR. It is nothing new or novel. There are quite a few papers about this one. In most of the battery powered applications, something similar is used to convert the high battery output to 3V or 1.2V level., in which case every transistor except the pass transistor and it's diode will be low voltage transistors (Clearly there the intention is not high psrr but separating two voltage domains)
May I know what makes you think that this will need a min load current to work?

 

[dick_freebird]

At very low load currents the output cap and low conductance
swing the output pole too low and it becomes dominant.
And if the output overshoots there's nothing but a high
impedance to bring it back, turning a small signal stability
problem into a large-signal one.

Some LDOs include a sink transistor to provide a minimum
output conductance and provide a pulldown capability.