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How to improve LDO's transient response?

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Apr 2, 2006
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ldo transient response

I am now working on capacitor-less LDO (internal compensation,without large output capacitor)

The phase margin is about 57deg,and the unity-gain bandwidth is about 3.6MHz
I think it is stable enough.

When I simulate the load transient response,changing the load current from 1mA to 30mA,the voltage overshoot and undershoot both are around 160mV,which is too large. But the output settles in only less than 2us. How can I reduce the overshoot and undershoot?

capless ldo

Decrease the ac impedance the load current flow through. Sharp load current variation can load on the impedance to generate large voltage variation.

ldo overshoot

have you run the AC when the load is 30mA?

robert j milliken thesis

check the miniphase to see if it is much smaller than your PM.

ldo load response

Increase the Output Cap

insufficient transient response ldo

To lijianheng:
I don't quite understand you.Can you please explain in detail

To sunking:
I have run AC simulation when load current is 1mA and 30mA,the PM is at least 55deg.

I still can't find the reason,seek for help,thanks!
ldo transient setting

check for your error amplifier's output impedance. Are you using Miller effect capacitor to stabilize your system ? If it is, maybe you should increase the on-chip capacitor (maybe up to 2~3 pF) with a decent gain about 40 dB. Also try reduce your parasitic capacitance (pmos pass transistor) minimizing ntub area and stacking it to improve area efficiency, and use the bulk effect so you can give enough output current much faster than without using it.

cap-free ldo

again to get better performance u have to options : one to increase the loop GBW by increasing the gm of the error amplifier this will not decrease the overshoot but will enhance the settling
two increase the output cap. this will decrease the overshoot (I=C*dV/dt) so increasing the Cap decrease the voltage overshoot fort for the same I pulse capless ldo

To safwatonline:
Thanks! but usually on-chip capacitor can not be too large,what is the acceptable output capacitor value?

To arghpok:
The dominant pole is on the output of error amplifier due to miller compensation.The miller capacitor is 3pF.And I am using folded cascode as my error amplifier,the output impedance is large enough.The loop gain at DC is 100dB.
Are these value reasonable?

And I don't understand how to use bulk effect?

ldo transient response normal

Decrease the output impedence I mean,

For your case main pole is the output of error amp,

As you said you have add a miller cap 3pF that is large enough, it can feed the output ac voltage back to the gate of PMOSFET pass element, which is divide by the Cgs of the PMOSFET, multi by PMOSFET gm can generate ac current to make the transient response faster.

For more feedback ac voltage, you can try to minimize the area of PMOSFET to minimize the Cgs.

Another way to decrease output impedence is to add a cap at the output, you can use moscap to minimize its area.But in my opinion, because of the miller cap feedback, the output cap impedence can not be small enough until GHz range (for 10pF as a instance).

To enlarge the gainbandwidth is also a method to make transient responce faster, but it need large power consumption, and loop stability is also a consideration.

Use fast transient loop maybe not useful for your case main pole is at error amp output.


ldo phase margin overshoot

the cap range should be nearly 100pF-150pF, more is better!

emproved load transient response

well,I found that even if the output capacitor is more than 100pF,the transient overshoot is still larger than 100mV,why??

btw,I have adjust the miller cap in order to get PM around 60deg

things to improve in ldo

You have to decrease the output impedance, not increase it. That's because de pole frequency is inversely proportional to the impedance of the error amplifier. One useful technique is the simple buffer stage. When I talk about the Miller capacitor, I mean the mirroring technique to increase on-chip capacitance developed by Robert. Milliken on Texas A&M. You can find his Ms.C. thesis easily on the web.

You can use the bulk effect because it helps to reduce the threshold voltage, so you don't have to push too much gate drive in order to generate the necessary output current. <I have and idea about it, but I'm not gonna publish it until I have studied a little bit deeper and win the first Nobel prize on electronics (LOL)>. With that gain I'm sure you have pretty good line & load regulation, and you may sacrifice some of that to obtain better transient performance.


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ldo quick output capacitor discharge

Thanks to arghpok! The idea of bulk effect is good:)

And I have a quick glance at Robert. Milliken's Ms.C thesis, and found that actually he faced the similar problem,in worst case,the load transient undershoot is 214mV in his design.
So I think it may be a general problem due to small output capacitance,then my question is how much overshoot/undershoot can be tolerated in an LDO? Can somebody give application requirements,such as in digital blocks or analog/RF blocks?

robert milliken ldo

i don't get what you mean by bulk effect, please explain more

cap free ldo

Which are your new measurements under the modifications I've suggested ?

Have you used some of your 100 dB DC gain to improve your transient response ?
How long are those transient peaks ? How many Iq is your circuit using ?

It would help to post some of your simulations results zooming at the area of interest and also some of the circuit topology (specially the output stage), so we can suggest maybe a better architecture.

If you can afford 100+ uA of Iq, then you should decrease under/overshoot to around 50~100 mV.

ldo frequency and transient response

Some commercial chips like TI's add comparators to control overshoot and undershoot. When undershoot is detected, sourcing current will be increased and when overshoot is detected, a sinking current will pull low the output.
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ldo improve load regulation

You can thank me reporting my message gg

reduce overshoot in ldo

For digital circuits down to 0.13 um technology with the 1.2 voltage supply, I do not think 150 mV undershoot or overshoot will be a big problem. I am not sure if it is tolerable for those sensitive analog and RF circuits.

Added after 6 minutes:

The idea of bulk effect might help , however it can not solve the problem from the root.

The undershoot and overshoot is normal since there very small cap at the output to provide the fast load current transients or spikes.

Normally the bandwidth of the cap-less or cap-free LDO has to be higher than those with large output capacitor in order to achieve the same undershoot or overshoot specs.

Added after 12 minutes:

Using the emergency block to solve the special case (large undershoot or overshoot happens) just as Leo_2 said is always good solution in industry and engineering world. however it might not interesting in academic field.


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reducing undershoot comparator

OP_amp + Nmos fast response .but have volt limt

OP_amp + Pmos low speed ...

Ti have some paper tal about dymanic loading
maybe you can modify you regulator
add fast response path in OP_AMP .. speed up response time

if you have NPN (some Hi volt process have Vnpn) .. it will better than Pmos

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