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How to improve efficiency in VHDL ?

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Anuja Diggikar

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I developed adaptive filter for acoustic noise cancellation in VHDL which needs 3 multipliers. final output i got is errored sound. I want it error free. I think it is because i forward only MSB data of multiplier (as multiplier doubles data width ) . so some data get lost. is there any another solution instead of taking only msb data?
pl. help ?
Thank you in adv.
Diggikar
 
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ckshivaram

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what is your requirement,......... first learn to post the requirement in complete details ,, so that it avoids our guess work and save both people time............
 

Anuja Diggikar

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Actually data posted was incomplete by mistake. I modified it. pl. go through it and help.
Thank you for quick reply
 

FvM

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It sounds like a problem of not thinking about number ranges in signal processing with integer arithmetic. It's not particularly related to VHDL, I think. You should be able to reproduce the issue using pencil and paper or with a pocket calculator as well.

To discuss the VHDL related part, you should post the VHDL code including signal definitions.

P.S.: Did you consider, that the internal signals of a filter (and possibly the output as well) may need a larger numeric range than the input signal, depending on the filter transfer function? So designing suitable numeric ranges for all signals involved with a filter is strongly suggested. If an overflow can't be avoided in some cases, you possibly would want to add saturation logic to the arithmetic rather than accept a signal polarity reversal.
 
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