How to implement the four phase clock in digital logic?

[gunpla]

Dear All:

as the figure, i need four phase control clock

but i would like to implement in digital logic (like FF or logic gate)

who can tell me the search name or schematic ?

thanks

 

[SkyHigh]

You should implement this quad-phase clock generator in HDL like Verilog or VHDL.

Using discrete logic gates and FFs will surely incur races, delays and glitches.

 

[gunpla]

Thanks for SkyHigh

but i must use full-custom flow to implement this block

 

[Kral]

gunpla,
One way:
Implement a 2 stage shift counter by feeding the inverted output of the last stage of the shift register to the input of the first stage. This generates the following sequence:
00
10
11
01
Decode each output using 2-input And gates (Assuming that the complement of each stage is available). This sequence guarantees glich-free decoding because in going from one state to the next, one and only one bit changes state. This type of counter is called a "Johnson Counter". It can be implemented using any number of stages. It has the property that any state can be decoded in a glitch-free manner using 2-input And gates (Assuming that the complement of each stage is available). Furthermore, any consecutive sequence of states can also be glitch- free decoded using only 2-input And gates. The Johnson counter has the disadvantage of having only 2N states, as opposed to 2^N states for a binary counter. Also, if the counter ever gets into an illegal state, it will never get out, unless additional logic is provided. This, of course, can't happen with the 2 stage counter, since there are no illegal states.
Regards,
Kral

 

[sunking]

a counter can help you.