how to implement testbench and top level portmap?

[kumuking]

Recently I've almost finished a assignment.

**broken link removed**

But when I think I was done, problem came to me.
When I simulate the top level port map vhdl codes, nothing worked. I have attached a picture which is the simulation.

**broken link removed**

I think my codes are right. And I also set a configuration to relate the binding information between component and library.

I also attached 1 zip file which including 4 vhdl codes.
The assi8.vhd is the top level port map codes.
The assi8a.vhd is the testbench codes.
The assi8b.vhd is the module1 codes.
The assi8c.vhd is the module2 codes.

And I've googled a lot about the top level port map, but I found nothing to solve my problem.
Could you tell me how to solve the problem?
Thank you very much.

View attachment VHDL.zip

 

[kumuking]

I solve it by myself.
I found if I add binding information into the prot map, the codes will work.
For exmaple, I change

TESTBENCH_MAP: testbench
port map(

to

TESTBENCH_MAP: entity work.assi8a
port map(

So I think I didn't study well in VHDL. I have to re-study them from basic knowledge.

 

[TrickyDicky]

It looks like you ran your top level on its own and not your testbench. You need to instantiate the top level inside a testbench and create the signals inside the testbench to drive the IO signals.

Eg. for a clock, you can do this in a testbench:

signal clk : std_logic := '0' ;  ---Initialisation is important!

....
clk <= not clk after 10 ns; --modify clock period to taste. This produces a 50Mhz clock