How to implement SRAM with standard logic (DFF)?

[newcpu]

Hi,

I want to replace those small SRAM/Register File compiled by memory compiler with standard logic (DFF). Could you help to provide some references?

Thanks a lot.

Best Regards,
Newcpu

 

[lostinxlation]

Have a bunch of flops with write enables and output muxes.

 

[qieda]

see
https://www.edaboard.com/threads/198795/

 

[ic98]

See Leblebici's book on Digital IC Design

 

[newcpu]

Are there any simple method to verify the verilog code for this?
Thanks a lot.

 

[newcpu]

How to design the decode logic for address?
Thanks a lot.