How to implement interrupt in a 5-stage pipeline?

[shotgun_boy]

I am designing a 5-stage pipeline core. It has multi-cycle instructions, how to implement exact interrupt?
when to detect interrupt and how process with it?
thanks

 

[dd2001]

Any suggestion?

I have same problem, and want to have someone help. The big clue for me is why Intel can make 2GHz CPU on 0.18um siliconm and I only make 400MHz speed on same silcon, where is the big secret. Pipeline is a issue but whole.