Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to implement interrupt in a 5-stage pipeline?

shotgun_boy

Newbie level 6
Newbie level 6
Joined
Dec 26, 2002
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
6
I am designing a 5-stage pipeline core. It has multi-cycle instructions, how to implement exact interrupt?
when to detect interrupt and how process with it?
thanks
 
Any suggestion?

I have same problem, and want to have someone help. The big clue for me is why Intel can make 2GHz CPU on 0.18um siliconm and I only make 400MHz speed on same silcon, where is the big secret. Pipeline is a issue but whole.
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top