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How to implement a ultra jitter clock interface?

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DZC

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Hi, I want to implement a circuit to carry the clock in the chip out of the chip.
The jitter spec is less than 1ps and the clock frequency is 20M~500MHz.
I'm considering to use the Current Mode Logic and the LVDS interface.

My question is:does the LVDS interface capable of ensure such low jitter??
Or do you have any better suggeations?

Thanks a lot in advance!
 

leo_o2

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How to implement a ultra jitter output?

PLL or DLL?
 

    DZC

    points: 2
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