How to implement a ultra jitter clock interface?

[DZC]

Hi, I want to implement a circuit to carry the clock in the chip out of the chip.
The jitter spec is less than 1ps and the clock frequency is 20M~500MHz.
I'm considering to use the Current Mode Logic and the LVDS interface.

My question is:does the LVDS interface capable of ensure such low jitter??
Or do you have any better suggeations?

Thanks a lot in advance!

 

[leo_o2]

How to implement a ultra jitter output?

PLL or DLL?