How to implement a divider by VHDL?

[vkchau]

vhdl divider

I want to implement a divider in VHDL, operands are std_logic_vector(). How can I do it?
Thanks.

 

[gnomix]

divider vhdl

I want to implement a divider in VHDL, operands are std_logic_vector(). How can I do it?
Thanks.

Try this one.

 

[tlp71@hotmail.com]

vhdl divide

is not too hard.
You mest create a counter, and take une decode from this counter as output for your clock, if you resamople this whit the master clock is better.
And if you try is also happy.
bye.
G.

 

[radix]

divide in vhdl

vkchau,

A little more info would be useful.

Are you trying to divide down a single signal, such as a clock, or do you want to divide a value (8-bit, 16-bit, ...)?

What value do you need to divide by? Is the divisor a multiple of 2 or something else?

Radix

 

[ydao]

divide vhdl

do want to implement your logic model by asic/fpga? or just to ask the statement of divide in VHDL?

 

[cyberdome]

divider in vhdl

Hi,

It is quite simple to implement a divider using a bit iterative algorithm, given that you have the time to do it iterative. I implemented one using a shift-subtract-compare method. The way I did it, it calculated one bit in the quotient in each iteration. This method only works for unsigned operands, so if you need signed operands you have to use some tricks.
It shouln't be too hard to find some info about divider algorithms using google.

Good luck!
/cyberdome