How to implement a counter by only using logic gates?

[Hassanf]

Could do with some help.

Hello I'am kinda new to CPLD programming. I was wondering how to implement a counter that can count fron 0-9 by only using flip-flops and other logic gates. I will be highly oblighed if some-one can point me out to the right direction or offer form any assistance. Thank you.

 

[salma ali bakr]

Re: Could do with some help.

i am not sure really but

u can write the FF code in an HDL (VHDL or verilog)...from any book (cause u must have the internal architecture of the FF...

and make 4 components from that FF (cause u need to have 4bits in order to count from 0 till 9)...then reset all the FF using "and gate" for instance before it counts to 10 (when the count is "1010")...so u should put an inverter before the first and third bits (given that u start with bit zero) in order to have a zero as the and output to reset the FFs...u should know that well if u took logic design...

that is all....good luck

Salma

 

[Iouri]

Could do with some help.

This is interesting one! I mean all digigatal stuff will be implimeted using logic gates and flip flops registers, counters and etc.. Could you please be more specific what are you looking?

Regards,

 

[Hassanf]

Re: Could do with some help.

I'am allowed to use flip flop registers and logic gates but not the actual counters itself. I kinda came up with the idea that if I have a 4 bit register with a incrementer it will be a counter. I will include the schematic here I would be highly obliged if someone can point out my mistakes or help me someother way.

 

[rishirameshkashyap]

Re: Could do with some help.

For that u have to design a MOD-10 counter which counts from 0-9, i.e 0000 to 1010 each bit repersents a Flip-Flop, as that count changes from 1001 to 1010 on the clk edge AND the O/P of 3 AND 1 st FF (i am counting 3 to 0 FF)and provide it to the input of clr . If any further help is required do feel free .