How to handle the asynchronous paths in the design

[owen_li]

Hi guys.

Are there any constraints for the physical designers to handle the asynchronous paths ? or just leave them "false paths"
Should we add some more constraints on these paths to insure the correct function of asynchronous paths ?
Thank you very much!

 

[yx.yang]

There is another constraint: set_max_delay.
For example: set_max_delay -from [get_clocks ??] -to [get_clocks ??]

 

[gaobin0628]

good answer

 

[owen_li]

I have a comment.
If we just use the "set_max_delay .......", how should I insure that the data and control signal will be captured by same cycle. Even thoughthe path meet the "max delay" requirement. They will be also be failed when the data and control come in a
different clock cycle.
thanks.