s3034585
Full Member level 4
vhdl addition
Hi Guys
Can anyone pls tell me how to do binary addition with vectors...
i tried to do but it gives me a error as "Type error resolving infix expression "+" as type std_logic_vector."
Hi Guys
Can anyone pls tell me how to do binary addition with vectors...
i tried to do but it gives me a error as "Type error resolving infix expression "+" as type std_logic_vector."
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Library IEEE; Use Ieee.std_logic_1164.all; entity add is Port( a: in std_logic_vector(3 downto 0) ; sum:out std_logic_vector(3 downto 0) ); end add; architecture behav of add is signal tmp : std_logic_vector(3 downto 0); begin tmp <= a(0) + a(1) +a(2) + a(3) when en = '1' else "0000"; sum <= tmp; end behav;
Last edited by a moderator: